Implementing a MIPS processor using SME

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

The Synchronous Message Exchange (SME) model, is a programming model, which closely resembles the CSP model and which is suitable for describing hardware. This paper aims to combine the theory taught in a machine architecture class, with the SME model, by implementing a MIPS processor using SME. I show how to construct the components of a MIPS processor as SME processes, and how to connect them by using SME busses. Furthermore, I show how to extend the processor, by introducing additional instructions and by pipelining the processor.

Original languageEnglish
Title of host publicationCommunicating Process Architectures 2017 and 2018, WoTUG-39 and WoTUG-40 - Proceedings of CPA 2017 (WoTUG-39) and Proceedings of CPA 2018 (WoTUG-40)
EditorsJan Baekgaard Pedersen, Kevin Chalmers, Jan F. Broenink, Brian Vinter, Kevin Vella, Peter H. Welch, Marc L. Smith, Kenneth Skovhede
PublisherIMIA and IOS Press
Publication date1 Jan 2019
Pages199-226
ISBN (Electronic)9781614999485
DOIs
Publication statusPublished - 1 Jan 2019
Event39th WoTUG Conference on Communicating Process Architectures, CPA 2017 and 40th WoTUG Conference on Communicating Process Architectures, CPA 2018 - Dresden, Germany
Duration: 19 Aug 201822 Aug 2018

Conference

Conference39th WoTUG Conference on Communicating Process Architectures, CPA 2017 and 40th WoTUG Conference on Communicating Process Architectures, CPA 2018
LandGermany
ByDresden
Periode19/08/201822/08/2018
SeriesConcurrent Systems Engineering Series
Volume70
ISSN1383-7575

    Research areas

  • FPGA, Hardware, MIPS, SME, VHDL

ID: 239622966