Mitigated FPGA design of multi-gigabit transceivers for application in high radiation environments of High Energy Physics experiments
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Mitigated FPGA design of multi-gigabit transceivers for application in high radiation environments of High Energy Physics experiments. / Brusati, M.; Camplani, A.; Cannon, M.; Chen, H.; Citterio, M.; Lazzaroni, M.; Takai, H.; Wirthlin, M.
I: Measurement: Journal of the International Measurement Confederation, Bind 108, 2017, s. 171-192.Publikation: Bidrag til tidsskrift › Tidsskriftartikel › Forskning › fagfællebedømt
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TY - JOUR
T1 - Mitigated FPGA design of multi-gigabit transceivers for application in high radiation environments of High Energy Physics experiments
AU - Brusati, M.
AU - Camplani, A.
AU - Cannon, M.
AU - Chen, H.
AU - Citterio, M.
AU - Lazzaroni, M.
AU - Takai, H.
AU - Wirthlin, M.
N1 - Publisher Copyright: © 2017 Elsevier Ltd
PY - 2017
Y1 - 2017
N2 - SRAM-based Field Programmable Gate Array (FPGA) logic devices are very attractive in applications where high data throughput is needed, such as the latest generation of High Energy Physics (HEP) experiments. FPGAs have been rarely used in such experiments because of their sensitivity to radiation. The present paper proposes a mitigation approach applied to commercial FPGA devices to meet the reliability requirements for the front-end electronics of the Liquid Argon (LAr) electromagnetic calorimeter of the ATLAS experiment, located at CERN. Particular attention will be devoted to define a proper mitigation scheme of the multi-gigabit transceivers embedded in the FPGA, which is a critical part of the LAr data acquisition chain. A demonstrator board is being developed to validate the proposed methodology. Mitigation techniques such as Triple Modular Redundancy (TMR) and scrubbing will be used to increase the robustness of the design and to maximize the fault tolerance from Single-Event Upsets (SEUs).
AB - SRAM-based Field Programmable Gate Array (FPGA) logic devices are very attractive in applications where high data throughput is needed, such as the latest generation of High Energy Physics (HEP) experiments. FPGAs have been rarely used in such experiments because of their sensitivity to radiation. The present paper proposes a mitigation approach applied to commercial FPGA devices to meet the reliability requirements for the front-end electronics of the Liquid Argon (LAr) electromagnetic calorimeter of the ATLAS experiment, located at CERN. Particular attention will be devoted to define a proper mitigation scheme of the multi-gigabit transceivers embedded in the FPGA, which is a critical part of the LAr data acquisition chain. A demonstrator board is being developed to validate the proposed methodology. Mitigation techniques such as Triple Modular Redundancy (TMR) and scrubbing will be used to increase the robustness of the design and to maximize the fault tolerance from Single-Event Upsets (SEUs).
KW - FPGA
KW - High Energy Physics
KW - Instrumentation
KW - Measurement
KW - Reliability
KW - Scrubbing
U2 - 10.1016/j.measurement.2017.02.025
DO - 10.1016/j.measurement.2017.02.025
M3 - Journal article
AN - SCOPUS:85014247808
VL - 108
SP - 171
EP - 192
JO - Measurement: Journal of the International Measurement Confederation
JF - Measurement: Journal of the International Measurement Confederation
SN - 0263-2241
ER -
ID: 309282204