An architecture for a mitigated FPGA multi-gigabit transceiver for high energy physics environments

Research output: Contribution to conferencePaperResearchpeer-review

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An architecture for a mitigated FPGA multi-gigabit transceiver for high energy physics environments. / Brusati, M.; Camplani, A.; Cannon, M.; Chen, H.; Citterio, M.; Lazzaroni, M.; Takai, H.; Wirthlin, M.

2016. 370-376 Paper presented at 14th IMEKO TC10 Workshop on Technical Diagnostics 2016: New Perspectives in Measurements, Tools and Techniques for Systems Reliability, Maintainability and Safety, Milan, Italy.

Research output: Contribution to conferencePaperResearchpeer-review

Harvard

Brusati, M, Camplani, A, Cannon, M, Chen, H, Citterio, M, Lazzaroni, M, Takai, H & Wirthlin, M 2016, 'An architecture for a mitigated FPGA multi-gigabit transceiver for high energy physics environments', Paper presented at 14th IMEKO TC10 Workshop on Technical Diagnostics 2016: New Perspectives in Measurements, Tools and Techniques for Systems Reliability, Maintainability and Safety, Milan, Italy, 27/06/2016 - 28/06/2016 pp. 370-376.

APA

Brusati, M., Camplani, A., Cannon, M., Chen, H., Citterio, M., Lazzaroni, M., Takai, H., & Wirthlin, M. (2016). An architecture for a mitigated FPGA multi-gigabit transceiver for high energy physics environments. 370-376. Paper presented at 14th IMEKO TC10 Workshop on Technical Diagnostics 2016: New Perspectives in Measurements, Tools and Techniques for Systems Reliability, Maintainability and Safety, Milan, Italy.

Vancouver

Brusati M, Camplani A, Cannon M, Chen H, Citterio M, Lazzaroni M et al. An architecture for a mitigated FPGA multi-gigabit transceiver for high energy physics environments. 2016. Paper presented at 14th IMEKO TC10 Workshop on Technical Diagnostics 2016: New Perspectives in Measurements, Tools and Techniques for Systems Reliability, Maintainability and Safety, Milan, Italy.

Author

Brusati, M. ; Camplani, A. ; Cannon, M. ; Chen, H. ; Citterio, M. ; Lazzaroni, M. ; Takai, H. ; Wirthlin, M. / An architecture for a mitigated FPGA multi-gigabit transceiver for high energy physics environments. Paper presented at 14th IMEKO TC10 Workshop on Technical Diagnostics 2016: New Perspectives in Measurements, Tools and Techniques for Systems Reliability, Maintainability and Safety, Milan, Italy.7 p.

Bibtex

@conference{8cae00ba4d714ea0a3e6609541a23bf9,
title = "An architecture for a mitigated FPGA multi-gigabit transceiver for high energy physics environments",
abstract = "SRAM-based Field Programmable Gate Array (FPGA) logic devices are very attractive in applications where high data throughput is needed, such as the latest generation of High Energy Physics (HEP) experiments. FPGAs have been rarely used in such experiments because of their sensitivity to radiation. The present paper proposes a mitigation approach applied to commercial FPGA devices to meet the reliability requirements for the front-end electronics of the Liquid Argon (LAr) electromagnetic calorimeter of the ATLAS experiment, located at CERN. Particular attention will be devoted to define a proper mitigation scheme of the multi-gigabit transceivers embedded in the FPGA, which is a critical part of the LAr data acquisition chain. A demonstrator board is being developed to validate the proposed methodology. Mitigation techniques such as Triple Modular Redundancy (TMR) and scrubbing will be used to increase the robustness of the design and to maximize the fault tolerance from Single-Event Upsets (SEUs).",
author = "M. Brusati and A. Camplani and M. Cannon and H. Chen and M. Citterio and M. Lazzaroni and H. Takai and M. Wirthlin",
note = "Publisher Copyright: {\textcopyright} 2016, IMEKO-International Measurement Federation Secretariat. All rights reserved.; 14th IMEKO TC10 Workshop on Technical Diagnostics 2016: New Perspectives in Measurements, Tools and Techniques for Systems Reliability, Maintainability and Safety ; Conference date: 27-06-2016 Through 28-06-2016",
year = "2016",
language = "English",
pages = "370--376",

}

RIS

TY - CONF

T1 - An architecture for a mitigated FPGA multi-gigabit transceiver for high energy physics environments

AU - Brusati, M.

AU - Camplani, A.

AU - Cannon, M.

AU - Chen, H.

AU - Citterio, M.

AU - Lazzaroni, M.

AU - Takai, H.

AU - Wirthlin, M.

N1 - Publisher Copyright: © 2016, IMEKO-International Measurement Federation Secretariat. All rights reserved.

PY - 2016

Y1 - 2016

N2 - SRAM-based Field Programmable Gate Array (FPGA) logic devices are very attractive in applications where high data throughput is needed, such as the latest generation of High Energy Physics (HEP) experiments. FPGAs have been rarely used in such experiments because of their sensitivity to radiation. The present paper proposes a mitigation approach applied to commercial FPGA devices to meet the reliability requirements for the front-end electronics of the Liquid Argon (LAr) electromagnetic calorimeter of the ATLAS experiment, located at CERN. Particular attention will be devoted to define a proper mitigation scheme of the multi-gigabit transceivers embedded in the FPGA, which is a critical part of the LAr data acquisition chain. A demonstrator board is being developed to validate the proposed methodology. Mitigation techniques such as Triple Modular Redundancy (TMR) and scrubbing will be used to increase the robustness of the design and to maximize the fault tolerance from Single-Event Upsets (SEUs).

AB - SRAM-based Field Programmable Gate Array (FPGA) logic devices are very attractive in applications where high data throughput is needed, such as the latest generation of High Energy Physics (HEP) experiments. FPGAs have been rarely used in such experiments because of their sensitivity to radiation. The present paper proposes a mitigation approach applied to commercial FPGA devices to meet the reliability requirements for the front-end electronics of the Liquid Argon (LAr) electromagnetic calorimeter of the ATLAS experiment, located at CERN. Particular attention will be devoted to define a proper mitigation scheme of the multi-gigabit transceivers embedded in the FPGA, which is a critical part of the LAr data acquisition chain. A demonstrator board is being developed to validate the proposed methodology. Mitigation techniques such as Triple Modular Redundancy (TMR) and scrubbing will be used to increase the robustness of the design and to maximize the fault tolerance from Single-Event Upsets (SEUs).

UR - http://www.scopus.com/inward/record.url?scp=84985911294&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:84985911294

SP - 370

EP - 376

T2 - 14th IMEKO TC10 Workshop on Technical Diagnostics 2016: New Perspectives in Measurements, Tools and Techniques for Systems Reliability, Maintainability and Safety

Y2 - 27 June 2016 through 28 June 2016

ER -

ID: 309282391