Master defense by Mikkel Møller Mødekjær

Title: Heterogeneous implementation of Machine Learning pathfinder, for the ATLAS trigger system for the High-Luminosity Large Hadron Collider upgrade

Abstract: The Large Hardon Collider is planning an upgrade, where the luminosity is getting an increase, which will produce more data, therefore the trigger and data acquisition system for the ATLAS experiment is getting an upgrade as well. 

The current software tracking process is challenging do to the combinatorics and running on CPU only, therefore we consider machine learning algorithms for track seeding. This is done to increase the runtime of the algorithm, to keep up with the new trigger system. These are tested to improve runtime and accuracy in the context of Event filter tracking project. 16 different models based on neural networks and 6 tree-based models are tested, on four different variations of the data. 

These variations are doing track seeding using a sliding window of 3 or 4 hits are used to predict the next, with versions going from inside the detector and outward, and from the outermost point inward. The models using the data with a seed of 4 hits and an approach from the outermost points inward in the detector produced the best results. Here the tree-based models outperform the neural network-based models, with the largest neural network-based being only slightly worse. In my tests, I verified that the model reconstructing track from the inside of the detector produced worse results than the other way, even with a change of the sliding windows size. Predicted values for the models using 16-bit calculations and data, produce almost the same results with a difference of less 1%, compared the 32-bit calculations.

In terms of runtime, the smaller models produced better results and the biggest model are slow to a point where it exceeds the timing constraints set on the system. This is gone through in detail in section 4.1. The tested hardware is CPU, GPU, and FPGA. Where GPU is the best at higher batch sizes, while FPGA outperforms at lower batch sizes.