Master Thesis defense by Sara Schjødt Kjær

Title: Implementation and optimisation of a Graph Neural Network-based track reconstruction pipeline on Intel FPGAs for the ATLAS TDAQ system for HL-LHC

Abstract: The Large Hadron Collider is undergoing the High Luminosity upgrade. With the accelerator upgrade comes an increase in the luminosity of particle collisions, and with that a factor 10 increase in the amount of data collected by the detectors. This puts entirely new demands on the computational power used for particle tracking in the ATLAS detector's TDAQ system.

This project explores the use of graph neural networks (GNNs) for fast and efficient online track reconstruction via implementation on Intel FPGAs. A three-step GNN-based track reconstruction pipeline has already been tested for offline track reconstruction, and is modified to fit the size constraints of an FPGA. We specifically consider FPGAs as the hardware host of the pipeline, due to its parallelism and low power consumption in comparison with GPUs and CPUs.

I explore two main areas of interest regarding the implementation of GNNs on FPGAs. Firstly, the size constraints of Intel FPGAs are studied by obtaining resource estimates for individual steps of the GNN pipeline. An estimate of the appropriate size of the pipeline steps is presented. Secondly, I explore how performance of the pipeline can be maintained whilst reducing its size to fit on an FPGA. I present methods for increasing performance, along with the track reconstruction efficiency obtained for a pipeline suited for FPGA implementation.