TY - JOUR

T1 - Gate reflectometry in dense quantum dot arrays

AU - Ansaloni, Fabio

AU - Bohuslavskyi, Heorhii

AU - Fedele, Federico

AU - Rasmussen, Torbjorn

AU - Brovang, Bertram

AU - Berritta, Fabrizio

AU - Heskes, Amber

AU - Li, Jing

AU - Hutin, Louis

AU - Venitucci, Benjamin

AU - Bertrand, Benoit

AU - Vinet, Maud

AU - Niquet, Yann-Michel

AU - Chatterjee, Anasua

AU - Kuemmeth, Ferdinand

PY - 2023/3/1

Y1 - 2023/3/1

N2 - Silicon quantum devices are maturing from academic single- and two-qubit devices to industrially-fabricated dense quantum-dot (QD) arrays, increasing operational complexity and the need for better pulsed-gate and readout techniques. We perform gate-voltage pulsing and gate-based reflectometry measurements on a dense 2 x 2 array of silicon QDs fabricated in a 300 mm-wafer foundry. Utilizing the strong capacitive couplings within the array, it is sufficient to monitor only one gate electrode via high-frequency reflectometry to establish single-electron occupation in each of the four dots and to detect single-electron movements with high bandwidth. A global top-gate electrode adjusts the overall tunneling times, while linear combinations of side-gate voltages yield detailed charge stability diagrams. To test for spin physics and Pauli spin blockade at finite magnetic fields, we implement symmetric gate-voltage pulses that directly reveal bidirectional interdot charge relaxation as a function of the detuning between two dots. Charge sensing within the array can be established without the involvement of adjacent electron reservoirs, important for scaling such split-gate devices towards longer 2 x N arrays. Our techniques may find use in the scaling of few-dot spin-qubit devices to large-scale quantum processors.

AB - Silicon quantum devices are maturing from academic single- and two-qubit devices to industrially-fabricated dense quantum-dot (QD) arrays, increasing operational complexity and the need for better pulsed-gate and readout techniques. We perform gate-voltage pulsing and gate-based reflectometry measurements on a dense 2 x 2 array of silicon QDs fabricated in a 300 mm-wafer foundry. Utilizing the strong capacitive couplings within the array, it is sufficient to monitor only one gate electrode via high-frequency reflectometry to establish single-electron occupation in each of the four dots and to detect single-electron movements with high bandwidth. A global top-gate electrode adjusts the overall tunneling times, while linear combinations of side-gate voltages yield detailed charge stability diagrams. To test for spin physics and Pauli spin blockade at finite magnetic fields, we implement symmetric gate-voltage pulses that directly reveal bidirectional interdot charge relaxation as a function of the detuning between two dots. Charge sensing within the array can be established without the involvement of adjacent electron reservoirs, important for scaling such split-gate devices towards longer 2 x N arrays. Our techniques may find use in the scaling of few-dot spin-qubit devices to large-scale quantum processors.

KW - spin qubits

KW - reflectometry

KW - quantum dots

KW - TOMOGRAPHY

KW - OPERATION

KW - PROCESSOR

KW - QUBITS

KW - LOGIC

U2 - 10.1088/1367-2630/acc126

DO - 10.1088/1367-2630/acc126

M3 - Journal article

VL - 25

JO - New Journal of Physics

JF - New Journal of Physics

SN - 1367-2630

IS - 3

M1 - 033023

ER -