Simultaneous operation of singlet-triplet qubits

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Standard

Simultaneous operation of singlet-triplet qubits. / Fedele, Federico; Chatterjee, Anasua; Kuemmeth, Ferdinand.

2019 Silicon Nanoelectronics Workshop, SNW 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8782937 (2019 Silicon Nanoelectronics Workshop, SNW 2019).

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Harvard

Fedele, F, Chatterjee, A & Kuemmeth, F 2019, Simultaneous operation of singlet-triplet qubits. in 2019 Silicon Nanoelectronics Workshop, SNW 2019., 8782937, Institute of Electrical and Electronics Engineers Inc., 2019 Silicon Nanoelectronics Workshop, SNW 2019, 24th Silicon Nanoelectronics Workshop, SNW 2019, Kyoto, Japan, 09/06/2019. https://doi.org/10.23919/SNW.2019.8782937

APA

Fedele, F., Chatterjee, A., & Kuemmeth, F. (2019). Simultaneous operation of singlet-triplet qubits. In 2019 Silicon Nanoelectronics Workshop, SNW 2019 [8782937] Institute of Electrical and Electronics Engineers Inc.. 2019 Silicon Nanoelectronics Workshop, SNW 2019 https://doi.org/10.23919/SNW.2019.8782937

Vancouver

Fedele F, Chatterjee A, Kuemmeth F. Simultaneous operation of singlet-triplet qubits. In 2019 Silicon Nanoelectronics Workshop, SNW 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8782937. (2019 Silicon Nanoelectronics Workshop, SNW 2019). https://doi.org/10.23919/SNW.2019.8782937

Author

Fedele, Federico ; Chatterjee, Anasua ; Kuemmeth, Ferdinand. / Simultaneous operation of singlet-triplet qubits. 2019 Silicon Nanoelectronics Workshop, SNW 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (2019 Silicon Nanoelectronics Workshop, SNW 2019).

Bibtex

@inproceedings{58e0b01feaa64a02ae07f763e2d36e25,
title = "Simultaneous operation of singlet-triplet qubits",
abstract = "We use fast gate-voltage pulses and multiplexed RF-reflectometry charge sensing to coherently manipulate and read out multiple singlet-triplet spin qubits, within a 2D array of 12 gate-defined quantum dots in GaAs. By measuring the qubits' responses to precise timing changes of control pulses generated at room temperature, we characterize in situ the synchronization of control pulses with sub-ns resolution. These techniques are useful for calibrating the effective delay in cryogenic transmission lines for silicon quantum processors.",
author = "Federico Fedele and Anasua Chatterjee and Ferdinand Kuemmeth",
year = "2019",
doi = "10.23919/SNW.2019.8782937",
language = "English",
series = "2019 Silicon Nanoelectronics Workshop, SNW 2019",
booktitle = "2019 Silicon Nanoelectronics Workshop, SNW 2019",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
note = "24th Silicon Nanoelectronics Workshop, SNW 2019 ; Conference date: 09-06-2019 Through 10-06-2019",

}

RIS

TY - GEN

T1 - Simultaneous operation of singlet-triplet qubits

AU - Fedele, Federico

AU - Chatterjee, Anasua

AU - Kuemmeth, Ferdinand

PY - 2019

Y1 - 2019

N2 - We use fast gate-voltage pulses and multiplexed RF-reflectometry charge sensing to coherently manipulate and read out multiple singlet-triplet spin qubits, within a 2D array of 12 gate-defined quantum dots in GaAs. By measuring the qubits' responses to precise timing changes of control pulses generated at room temperature, we characterize in situ the synchronization of control pulses with sub-ns resolution. These techniques are useful for calibrating the effective delay in cryogenic transmission lines for silicon quantum processors.

AB - We use fast gate-voltage pulses and multiplexed RF-reflectometry charge sensing to coherently manipulate and read out multiple singlet-triplet spin qubits, within a 2D array of 12 gate-defined quantum dots in GaAs. By measuring the qubits' responses to precise timing changes of control pulses generated at room temperature, we characterize in situ the synchronization of control pulses with sub-ns resolution. These techniques are useful for calibrating the effective delay in cryogenic transmission lines for silicon quantum processors.

U2 - 10.23919/SNW.2019.8782937

DO - 10.23919/SNW.2019.8782937

M3 - Article in proceedings

AN - SCOPUS:85070868191

T3 - 2019 Silicon Nanoelectronics Workshop, SNW 2019

BT - 2019 Silicon Nanoelectronics Workshop, SNW 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 24th Silicon Nanoelectronics Workshop, SNW 2019

Y2 - 9 June 2019 through 10 June 2019

ER -

ID: 241088894