Implementing a MIPS processor using SME
Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review
The Synchronous Message Exchange (SME) model, is a programming model, which closely resembles the CSP model and which is suitable for describing hardware. This paper aims to combine the theory taught in a machine architecture class, with the SME model, by implementing a MIPS processor using SME. I show how to construct the components of a MIPS processor as SME processes, and how to connect them by using SME busses. Furthermore, I show how to extend the processor, by introducing additional instructions and by pipelining the processor.
Original language | English |
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Title of host publication | Communicating Process Architectures 2017 and 2018, WoTUG-39 and WoTUG-40 - Proceedings of CPA 2017 (WoTUG-39) and Proceedings of CPA 2018 (WoTUG-40) |
Editors | Jan Baekgaard Pedersen, Kevin Chalmers, Jan F. Broenink, Brian Vinter, Kevin Vella, Peter H. Welch, Marc L. Smith, Kenneth Skovhede |
Publisher | IMIA and IOS Press |
Publication date | 1 Jan 2019 |
Pages | 199-226 |
ISBN (Electronic) | 9781614999485 |
DOIs | |
Publication status | Published - 1 Jan 2019 |
Event | 39th WoTUG Conference on Communicating Process Architectures, CPA 2017 and 40th WoTUG Conference on Communicating Process Architectures, CPA 2018 - Dresden, Germany Duration: 19 Aug 2018 → 22 Aug 2018 |
Conference
Conference | 39th WoTUG Conference on Communicating Process Architectures, CPA 2017 and 40th WoTUG Conference on Communicating Process Architectures, CPA 2018 |
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Land | Germany |
By | Dresden |
Periode | 19/08/2018 → 22/08/2018 |
Series | Concurrent Systems Engineering Series |
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Volume | 70 |
ISSN | 1383-7575 |
- FPGA, Hardware, MIPS, SME, VHDL
Research areas
ID: 239622966